1. Field of the Invention
This invention relates to a protection circuit for a semiconductor device such as a semiconductor integrated circuit (IC, LSI etc.), more particularly to a protection circuit provided in such a semiconductor device for protecting an internal circuit from high-surge voltages, such as those generated by static electricity, accidentally applied to a pad serving as a terminal for connection with an external circuit.
2. Description of the Related Art
Variously configured protection circuits are used to protect the internal circuitry of semiconductor devices from high-surge voltages, such as those generated by static electricity. One example is shown in FIG. 24.
FIG. 24 is a circuit diagram showing an example of the input circuit of a semiconductor device equipped with an ordinary protection circuit 9 and an internal circuit 3.
The protection circuit 9 is constituted of diodes 91, 92 and a resistor 4, while the internal circuit 3 is constituted of a P-channel metal-insulator-semiconductor (MIS) field effect transistor 1 and an N-channel MIS field effect transistor 2.
"MIS field effect transistor" is a general term encompassing field effect transistors of the metal-insulator-semiconductor structure, including MOS field effect transistors. It is abbreviated as MISFET in this specification.
In the input circuit of this semiconductor device, a pad 10 is connected to the anode of the diode 91 and one terminal of the resistor 4 constituting the protection circuit 9. The other terminal of the resistor 4 is connected to the cathode of the diode 92 and the gates of the P-channel MISFET 1 and the N-channel MISFET 2 constituting the internal circuit 3.
A first power supply terminal 11 is connected to one terminal of the P-channel MISFET 1 and the cathode of the diode 91, and a second power supply terminal 12 is connected to the other terminal of the N-channel MISFET 2 and the anode of the diode 92.
The first power supply terminal 11 is supplied with a base voltage (VDD) and the second power supply terminal 12 is supplied with a negative supply voltage (VSS).
The other terminal of the P-channel MISFET I and the other terminal of the N-channel MISFET 2 are both connected to an output terminal 13.
The protection circuit 9 is required to protect the internal circuit 3 from several KV to ten-pius KV of static electricity of either polarity that may be accidentally applied to the pad 10.
When positive static electricity applied to the pad 10 reaches the connection point between the anode of the diode 91 and the resistor 4, the diode 91 turns on in the forward direction to pass current to the first power supply terminal 11. The voltage at which the diode 91 begins to pass this current is called the threshold voltage. Since the positive voltage applied to the pad 10 is clamped at the forward threshold voltage of the diode 91, no voltage higher than this forward threshold voltage is applied to the internal circuit 3.
When negative static electricity applied to the pad 10 reaches the cathode of the diode 92 through the resistor 4, the diode 92 turns on in the forward direction to pass current to the pad 10 through the resistor 4. Since the negative voltage applied to the pad 10 is therefore clamped at the forward threshold voltage of the diode 92, no voltage of an absolute value higher than this forward threshold voltage is applied to the internal circuit 3.
Since the resistor 4 is connected in series between the pad 10 and the internal circuit 3, it also serves to smooth sharply rising noise components produced by static electricity.
The shrinking dimensions of MISFETs in recent years has led to increasingly thin MISFET gate insulating films. Since a thinner MISFET gate insulating film exhibits lower breakdown strength, the importance of the protection circuit is greater than in the past.
The protection capability of the conventional protection circuit using two diodes as described in the foregoing is dependent on the area of the PN junctions of the diodes. In the semiconductor device shown in FIG. 24, for instance, the protection of the internal circuit 3 by the protection circuit 9 can be enhanced in terms of the breakdown strength of the MTSFETs 1 and 2 constituting the internal circuit 3 by increasing the area of the PN junctions of the diodes 91, 92 constituting the protection circuit 9.
This is because increasing the area of the PN junctions of the diodes 91, 92 enables the diodes 91, 92 to pass a greater amount of current per unit time and reduces the current passage per unit area of the PN junctions constituting the diodes 91, 92. As a result, the protection capability of the protection circuit increases.
Decreasing the amount of current passed per unit area of the PN junctions of the diodes 91, 92 also suppresses generation of heat by the current passing through the PN junctions. Since this prevents thermal breakdown of the diodes 91, 92, it prevents breakdown of the protection circuit 9 itself.
However, an attempt to secure these advantages by increasing the area of the PN junctions of the diodes 91, 92 leads to a major problem, namely, that it increases the area of the semiconductor device accounted for by the protection circuit 9.
In order to protect the internal circuit 3 by clamping high voltages applied to the pad 10 owing to static electricity, the protection circuit 9 of FIG. 24 requires a separate clamping element for voltage of each of the positive and negative polarities generated by static electricity and thus requires the two diodes 91, 92.
An attempt to improve the protection capability of the protection circuit by increasing the area of the PN junctions of the diodes serving as the clamping devices therefore greatly increases the area occupied by the protection circuit. Moreover, additional space is taken up by the power lines of opposite polarity required for enabling the two diodes to pass surge currents produced when high voltages occur.
This reduces the amount of space available in the vicinity of the pad 10 for provision of circuitry other than the protection circuit 9 and, in turn, increases the area of the semiconductor device as a whole. Since this way of increasing protection capability therefore runs counter to the desire to reduce semiconductor device area and lower cost, it is best avoided.
On the other hand, an attempt to prevent increase in the overall area of the semiconductor device by reducing the layout area of the protection circuit 9 thwarts securement of adequate area for the PN junctions of the diodes 91, 92 constituting the protection circuit 9 and therefore degrades the protection of the internal circuit 3 from static electricity applied to the pad 10. Since it also reduces the width of the power lines of the protection circuit 9 and thus lowers the current capacity thereof, it also increases the risk of the protection circuit 9 itself breaking down.
This has led to the use of the protection circuit 91 shown in FIG. 25, which is configured using the diode 91 as the only clamping element. When a high negative voltage is applied to the pad 10, the voltage is clamped at the breakdown voltage of the diode 91.
Since this configuration requires only a single clamping element and a power line of only one polarity for each pad, it enables the area of the PN junction of the diode serving as the clamping element to be increased and the durability of the power line to be enhanced by increasing its width.
However, in the case of the protection circuit 91, the clamp voltage at the time of application of positive voltage to the pad 10 is equal to the forward threshold voltage of the diode 91, but the clamp voltage at the time of application of negative voltage to the Dad 10 is equal to the breakdown voltage of the diode 91 (about 50 V) and is therefore fairly large. Another disadvantage of this arrangement is that the diode degenerates with repeated breakdown.
In view of the foregoing problems of the prior art, an object of this invention is to provide a protection circuit for a semiconductor device which by use of a single clamping element per pad and without employing breakdown enables reliable protection of an internal circuit when a high electrostatic voltage of either positive or negative polarity is applied to the pad of the semiconductor device, which does not constrain the area available in the semiconductor device for provision of a circuit other than the protection circuit, and which eliminates the risk of breakdown of the protection circuit itself.